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WM2148 14-bit 8MSPS Analogue-To-Digital Converter
Production Data, February 2001, Rev 1.1
DESCRIPTION
The WM2148 is a 14-bit, 8 MSPS analogue to digital converter with an on-chip voltage reference, high bandwidth sample and hold amplifier and programmable gain. The analogue input is differential, giving excellent commonmode noise immunity and low distortion. The WM2148 is designed for use in highly integrated, lowpower 3.3V systems. A high speed, microprocessor compatible parallel interface allows control of the ADC input gain, digital DC offset, internal / external reference and output data format. Both binary and two's complement formats are supported. The device also features an out of range indicator pin to show when the input signal exceeds the converter's full-scale range. In Power Down mode, all analogue circuitry is internally disconnected from the power supply, reducing total supply current to 20A. The WM2148 is available in a 1mm thin 48-pin TQFP package in standard commercial and industrial temperature ranges.
FEATURES
* * * * * * * * * * * * * 14-bit resolution ADC 8 MSPS conversion rate Differential input 3.3V single supply Very low current power down mode - 20A typical Microprocessor compatible parallel interface Internal or external voltage reference High bandwidth sample and hold amplifier - 140MHz full-power bandwidth Programmable Gain Amplifier (PGA) Programmable DC offset Binary or two's complement output format Out of range indicator 48-pin TQFP package, body thickness 1mm
APPLICATIONS
* * * * Communications xDSL Front ends Industrial control Instrumentation
BLOCK DIAGRAM
VBG
PRECISION REFERENCE
REF+ REF-
IN+
IN-
+ PGA -
D[13:0]
ADC
OUTPUT BUFFERS OVI
PARALLEL INTERFACE AND CONTROL LOGIC
WM2148
A[1:0] CSB WEB OEB CLK
WOLFSON MICROELECTRONICS LTD
Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2001 Wolfson Microelectronics Ltd.
WM2148 PIN CONFIGURATION ORDERING INFORMATION
DEVICE
DVDDCTRL
Production Data
TEMP. RANGE 0 to +70oC -40 to +85oC
PACKAGE 48-pin TQFP 1 mm thick body
WM2148CFT/V
NC CSB A1 NC A0
AGND2
AVSUB
AGND1
AVDD2
AVDD1
IN+
WM2148IFT/V
48 INAVDDREF VBG CML REF+ REFAGNDREF VSUB DGNDLOGIC OVI D13 D12 1 2 3 4 5 6 7 8 9 10 11 12 13
47
46
45
44
43
42
41
40
39
38
37 36 35 34 33 32 31 30 29 28 27 26 25 WRB OEB DGNDCTRL DGNDCLK CLK DVDDCLK DVDDLOGIC D0 D1 D2 DVDDOP2 DGNDOP2
14
15
16
17
18
19
20
21
22
23
24
DVDDOP1
D8
DGNDOP1
DVDDOP3
D9
D6
D5
D4
D11
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NAME INAVDDREF VBG CML REF+ REFAGNDREF VSUB DGNDLOGIC OVI D13 D12 D11 DVDDOP1 DGNDOP1 D10 D9 D8 D7 DVDDOP3 D6 D5 D4 D3 DGNDOP2 DVDDOP2 TYPE Analogue Input Supply Analogue I/O Analogue Output Analogue Output Analogue Output Supply Supply Supply Digital Output Digital I/O Digital I/O Digital I/O Supply Supply Digital I/O Digital I/O Digital I/O Digital I/O Supply Digital I/O Digital I/O Digital I/O Digital I/O Supply Supply DESCRIPTION Negative Differential Analogue Input Positive Supply Voltage for Reference Bandgap Voltage / External Reference Reference Decoupling Point Positive Reference Voltage Negative Reference Voltage Reference Block Ground Device Substrate Digital Ground for Logic Block Out of Range Indicator Data Bit 13 Data Bit 12 Data Bit 11 Positive Supply for Output Drivers Ground for Output Drivers Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Positive Supply for Output Drivers Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Ground for Output Drivers Positive Supply for Output Drivers
PD Rev 1.1 February 2001
WOLFSON MICROELECTRONICS LTD
D10
D7
D3
2
Production Data PIN 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Note: 1. It is recommended that each pair of supply pins, especially the analogue supplies, have a separate decoupling capacitor. The most critical are pins 46 and 47. The ADC substrate (pin 45) should be as noise free as possible. NAME D2 D1 D0 DVDDLOGIC DVDDCLK CLK DGNDCLK DGNDCTRL OEB WRB CSB NC NC A1 A0 DVDDCTRL AVDD1 AGND1 AVSUB AGND2 AVDD2 IN+ TYPE Digital I/O Digital I/O Digital I/O Supply Supply Digital Input Supply Supply Digital Input Digital Input Digital Input Test Output Test Output Digital Input Digital Input Supply Supply Supply Substrate Supply Supply Analogue Input Data Bit 2 Data Bit 1 Data Bit 0 Positive Supply Voltage for Logic Block Positive Supply Voltage for Clock Sample Clock Ground for Clock Ground for Control Pins Output Enable (active low) Write Signal (active low) Chip Select (active low) This pin must be left unconnected This pin must be left unconnected Address Bit 1 Address Bit 0 Positive Supply for Control Pins Positive Supply for ADC Ground for ADC ADC substrate Positive Supply for ADC Op-amps Ground for ADC Op-amps Positive Differential Analogue Input DESCRIPTION
WM2148
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WM2148 ABSOLUTE MAXIMUM RATINGS
Production Data
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112 and A113, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Analogue Supply Voltage (AVDD to AGND) Digital Supply Voltage (DVDD to DGND) Reference Input Voltage Range (VBG) Analogue Inputs Voltage Range Digital Inputs Voltage Range C suffix Operating temperature range (TA) Storage temperature Lead temperature (soldering 10 seconds, 1.6 mm from package body) I suffix MIN -0.3 -0.3 AGND -0.3V AGND -0.3V DGND -0.3V 0C -40C -65C MAX 4V 4V AVDD +0.3V AVDD +0.3V DVDD +0.3V +70C +85C +150C +260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltages (digital and analogue) Reference Input Voltage Digital Input HIGH Level Digital Input LOW Level Load Capacitance Clock Frequency Clock Duty Cycle Operating Free-air Temperature TA C Suffix I Suffix SYMBOL AVDD, DVDD VBG VIH VIL CL fCLK 0.1 40 0 -40 External reference TEST CONDITIONS MIN 3.0 1.425 2 TYP 3.3 1.5 3.3 0 5 8 50 25 25 0.8 15 8 60 70 85 MAX 3.6 1.575 UNIT V V V V pF MHz % C
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Production Data
WM2148
ELECTRICAL CHARACTERISTICS
Electrical characteristics over recommended temperature range, AVDD = DVDD = 3.3V (unless otherwise noted) PARAMETER Power Supplies Analogue Supply Current Digital Supply Current Power Consumption Power Down Supply Current (sum of all supply currents) DC Characteristics Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error AC Characteristics Analogue Input Bandwidth FIN = 100kHz Total Harmonic Distortion THD FIN = 1MHz FIN = 4MHz Signal to Noise Ratio Signal to Noise plus Distortion SNR SINAD SFDR ENOB VBG Internal reference FIN = 1MHz FIN = 4MHz FIN = 1MHz FIN = 4MHz Spurious Free Dynamic Range Effective Number of Bits Reference Voltage Bandgap Voltage Temperature Coefficient Supply Voltage Coefficient VBG Input Impedance Positive Reference Voltage Negative Reference Voltage Reference Voltage Difference Analog Inputs Positive Analogue Input Voltage Negative Analogue Input Voltage Input Voltage Difference Input impedance PGA Range PGA Step Size PGA Gain Error Digital Inputs Input LOW level Input HIGH level Input current Input capacitance VIL VIH IIN CIN 5 2 1 0.8 V V A pF VIN+ VINi 0 0 AVDD AVDD V V V k 7 1 0.25 dB dB dB VREF+ VREFi External reference VREF+ = VBG (1 + 2/3) VREF+ = VBG (1 - 2/3) 1.425 1.5 40 200 40 2.5 0.5 2.0 1.575 V ppm / C ppm / V k V V V FIN = 1MHz FIN = 4MHz 11.2 73 69 70 140 -81 -78 -77 72 71 70 70 80 80 11.5 bits dB dB dB dB MHz DNL INL Best Fit IN+ = IN-, 0dB gain 0 dB gain 14 0.6 3 1 5 0.3 1 bits bits bits % of FSR % of FSR AIDD DIDD P IPD = AIDD+DIDD AVDD = 3.6V DVDD = 3.6V AVDD = DVDD = 3.6V Power down mode CLK signal stopped 81 5 270 20 90 10 360 mA mA mW A SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
9REF
9REF = VREF+ VREFi
9IN
ZIN
9IN = VIN+ - VINi
- 9REF 25 0
9REF
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WM2148
Digital Outputs Output LOW level Output HIGH level High Impedance Output Current VOL VOH IOZ IOUT = -50A IOUT = +50A 2.6 10 0.4
Production Data
V V A
TERMINOLOGY
1. 2. DNL is the variation in the analogue step size associated with one digital output code across the input range, normalised to full scale. INL is the maximum deviation of the analogue input voltage associated with a digital code from its ideal value, normalised to full scale. Using the `best fit' method, ideal values are taken from a straight line fitted to the ADC curve. The INL figure thus obtained therefore characterises linearity only and is not affected by gain and offset errors. SNR is the ratio in dB of signal to noise amplitude when a full-scale sine wave is applied to the input. THD is the ratio in dB of the sum of all harmonics to signal amplitude when a full scale sine wave is applied to the input. SFDR is the amplitude ratio the output signal to the largest spur (artifact) produced by the device.
S1 S0 S5 S4 S2 S3 S7 S6 S8 S11 S12 S15 S16 S9 S10 S14
3. 4. 5.
S13
ANALOGUE INPUT
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Latency OUTPUT DATA
td S0 S1 S2 S3 S4 S5 S6
Figure 1 Latency PARAMETER Clock Timing Clock Frequency Output Delay Time Latency fCLK td CS = Low CS = Low CS = Low 9.5 0.1 8 8 25 MHz ns cycles SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
CSB tsu(OE-ACS) OEB ten D[0:13] DATA th(A) A[0:1] X ADDRESS X tdis th(CS)
Figure 2 Read Timing
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Production Data
WM2148
SYMBOL tsu(OE-ACS) ten tdis th(A) th(CS) TEST CONDITIONS CLoad = 15pF CLoad = 15pF CLoad = 15pF CLoad = 15pF CLoad = 15pF 1 0 10 MIN 4 15 TYP MAX UNIT ns ns ns ns ns
PARAMETER Read Timing Address and Chip select Setup Time Output Enable Output Disable Address Hold Time Chip select Hold Time Note: 1.
All timing parameters refer to a 50% level.
CSB tsu(WE-CS) WEB tsu(DA) D[0:13] X DATA X th(CS) A[0:1] X ADDRESS X th(CS)
Figure 3 Write Timing PARAMETER Write Timing Chip Select Setup Time Data and Address Setup Time Data and Address Hold Time Chip Select Hold Time Write Pulse Duration HIGH Note 1. Data is written to the addressed register at the rising edge of WEB. All timing parameters refer to a 50% level. tsu(WEi&6 tsu(DA) th(DA) th(CS) twH(WE) CLoad = 15pF CLoad = 15pF CLoad = 15pF CLoad = 15pF CLoad = 15pF 4 29 0 0 15 ns ns ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM2148 DEVICE DESCRIPTION
INTRODUCTION
Production Data
The WM2184 is a fast, low-power 14-bit ADC designed for leading edge telecommunications applications such as xDSL front-ends. It consists of a high bandwidth programmable gain input stage, a high resolution ADC, a parallel control interface, and internal voltage reference circuitry. Its fully differential design gives it excellent noise immunity. The analogue signal first enters the programmable gain amplifier (PGA), whose gain can be controlled in 1dB steps between 0dB and 7dB, using the PGA gain register. The signal is then digitised with respect to the two reference voltages, VREF+ and VREFi, in the ADC core. To compensate for DC offsets in the system, a programmable value of between -128 and +127 LSBs can be added to the digitised data. This is achieved by writing the offset value to the offset register and setting the DCO bit (bit 7) in the control register. Two different output formats are supported to suit the user's needs. In unsigned binary format, an allzero output represents the minimum analogue input level, while in two's complement format it refers to the middle level between minimum and maximum (see Table 1, below). ANALOGUE INPUT Minimum Midrange Maximum DIGITAL OUTPUT (Unsigned Binary) 0 8192 16383 DIGITAL OUTPUT (Two's Complement) -8192 0 8191
9IN = - 9REF 9IN = 0 9IN = 9REF
Table 1 Unsigned Binary vs Two's Complement Output Format The out-of-range indicator (OVI) output indicates that the analogue input signal is out of range. It is asserted whenever the differential input voltage 9IN exceeds the differential reference voltage 9REF or i9REF. This signal is updated simultaneously with the digital data outputs and is subject to the same pipeline delay. It can be used to adjust the gain of the internal PGA to prevent the ADC from clipping. The WM2148 incorporates a differential voltage reference circuit based on a 1.5V bandgap reference. The two reference voltages derived from the bandgap, VREF+ and VREFi, are two-thirds above and below the bandgap voltage VBG, at 2.5V and 0.5V respectively. The analogue input range is between the two references. To use an external reference, the on-chip bandgap circuit is disabled by setting the REF bit (bit 12) in the control register. The external reference voltage can then be applied at the VBG pin. VREF+ and VREFi are still buffered in the same by the internal reference amplifiers, such that:
2 VREF + = VBG x 1 + 3
and
2 V REF - = V BG x 1 - 3
For best performance, VBG, VREF+,VREFi and CML (reference midpoint, pin 4) should all be separately decoupled (see Recommended External Components). The WM2184 requires a single 3.3V supply voltage. In Power Down mode, the supply to all analogue circuitry in the device is switched off, reducing standby current to 20A provided that the clock is stopped (a running clock will increase the power consumption of the digital sections).
CONTROL INTERFACE
All functions of the WM2184 are accessed through its parallel interface. There are four internal registers to retrieve the ADC conversion data, set the device gain and DC offset, and control other features such as Power Down, reference voltage and output format. The parallel interface of the WM2148 features three-state buffers for direct connection to a shared data bus. Driving the OEB pin low enables the output buffers.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
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Production Data
WM2148
ADDRESS 0 1 2 3 A1 0 0 1 1 A0 0 1 0 1 REGISTER ADC Conversion Result PGA gain DC Offset Control
Table 2 WM2148 Internal Registers The ADC data register contains the result of the last analogue to digital conversion. It can also be used to reset the device to its default state by writing a `1' to the LSB (D0). This will set all the bits in the gain, offset and control registers to `0'. All other bits should always be set to zero when writing to the ADC data register. The PGA gain is controlled using the last three bits of Address 1. The eight possible binary values of 000 to 111 (decimal 7) correspond to a gain of 0 to 7dB, respectively. The lower byte of Address 2 holds the offset value (in LSBs). This value is added to the ADC data if the DCO bit in the Control register is set. The offset is in Two's complement format, providing a range of -128 to +127 LSB. REG. / BIT ADC Data PGA Gain DC Offset Control D13 MSB X X PWD D12 ... X X REF D11 ... X X FOR D10 ... X X TM2 D9 ... X X TM1 D8 ... X X TM0 D7 ... X MSB DCO D6 ... X ... X D5 ... X ... X D4 ... X ... X D3 ... X ... X D2 ... G2 ... X D1 ... G1 ... X D0 LSB/ SR G0 LSB X
Table 3 WM2148 Register Map The Control register (address 3) has four bits to program the device's operation and three test mode bits. Setting the Power Down bit (PWD) takes the device into Power Down mode. DCO enables the addition of the offset value held at Address 2 to the ADC output data. REF selects between internal and external reference voltages, and FOR between unsigned binary and Two's complement output format. BIT PWD REF FOR DCO SR X DESCRIPTION Power Down Reference Select Output Format DC Offset Software Reset Reserved 0 Normal Operation Internal Reference Unsigned Binary Enable Normal Operation 1 Power Down External Reference Two's Complement Disable Reset
Always set to 0 when writing to any register.
Table 4 Control Bits and Software Reset The ADC core can be tested by selecting one of six different test modes, which apply various voltages to the analogue inputs. This may be useful for calibration purposes. The test modes are controlled by the three test mode bits in the control register, TM0 to TM2 (see Table 5 below). TM2 0 0 0 0 1 1 1 1 Table 5 Test Modes TM1 0 0 1 1 0 0 1 1 TM0 0 1 0 1 0 1 0 1 FUNCTION Normal Operation Both inputs = REFIN+ at Vref/2, IN- at REFIN+ at REF+, IN- at REFNormal Operation Both inputs = REF+ IN+ at REF-, IN- at Vref/2 IN+ at REF-, IN- at REF+
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WM2148
PERFORMANCE DATA (TYPICAL)
284 282
DIDD+AIDD [mA] 90 80 70 60 50 40 30 20 10 0
Production Data
280 Power [mW] 278 276 274 272 270 268 0.1 1 Frequency [MHz] 10
0
50
100
150 time [ns]
200
250
300
Figure 4 Power Consumption vs Sample Clock
Figure 5 Supply Current vs Time (Power Down)
8 6 4
2 1.5 1 DNL (LSBs)
-6144 -4096 -2048 0 Code 2048 4096 6144
INL (LSBs)
2 0 -2 -4 -6 -8 -8192
0.5 0 -0.5 -1 -1.5 -2 -8192 -6144 -4096 -2048 0 Code 2048 4096 6144
Figure 6 Integral Nonlinearity at 8MSPS
Figure 7 Differential Nonlinearity at 8MSPS
-74 -76 -78 THD [dB] THD [dB] 10 100 1000 10000 -80 -82 -84 -86 -88 -90 Signal Frequency [kHz] at -1dB
-74 -76 -78 -80 -82 -84 -86 -88 -90 10 100 1000 10000 Signal Frequency [kHz] at -1dB
Figure 8 Total Harmonic Distortion at 3MSPS
Figure 9 Total Harmonic Distortion at 8MSPS
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Production Data
75 74 73 SNR [dB] SNR [dB] 72 71 70 69 68 67 10 100 1000 10000 Signal Frequency [kHz] at -1dB 75 74 73 72 71 70 69 68 67 10 100 1000
WM2148
10000
Signal Frequency [kHz] at -1dB
Figure 10 Signal to Noise Ratio at 3MSPS
Figure 11 Signal to Noise Ratio at 8MSPS
APPLICATION INFORMATION
DRIVING THE ANALOGUE INPUT
The WM2148 has a fully differential input. This is advantageous for signal to noise ratio, spurious free dynamic range, and harmonic distortion. It is recommended that the analogue input pins IN+ and IN- are connected as shown in Figure 12 below.
22 Ohms IN+ 100pF
DIFFERENTIAL ANALOGUE INPUT
WM2148
22 Ohms IN100pF
Figure 12 Recommended Input Configuration In this configuration, the ADC converts the difference 9IN of the two input signals VIN+ and VINi. The resistors and capacitors on the inputs decouple the driving source output from the ADC and also serve as first order low pass filters to reduce out of band noise. The input range on both inputs is 0V to AVDD. The full-scale value is determined by the voltage reference. The positive full-scale output is reached when 9IN equals 9REF, and the negative fullscale output is reached when 9IN equals -9REF.
9IN
-9REF 0
OUTPUT - full scale 0 + full scale
9REF
DIGITAL I/O
The digital outputs of the WM2148 are 3V CMOS compatible. In order to avoid current feedback errors, the capacitive load on these outputs should be as low as possible (maximum 15pF). Adding 100 series resistors on the digital outputs cam improve system performance by limiting the current during output transitions (this reduces noise on the power supplies).
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PD Rev 1.1 February 2001
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WM2148
RECOMMENDED EXTERNAL COMPONENTS
Production Data
AVDD 2
+
DVDD C2 C3 7 43 C4 C5 44 47 C6 C7 46 45 AVDD AGND AVDD AGND AVDD AGND AGND DVDD DGND DVDD DGND DVDD DGND DVDD 31 C9 33 30 C10 9 42 C11 34 14 C12 15 25 C13 26 20
+
C1
C8
AGND
AGND
DGND
DGND
AGND
DGND
AGND AGND
DGND
WM2148
48 1 IN+ IN-
DGND DVDD
DGND
DIFFERENTIAL ANALOGUE INPUT
DGND DVDD
DGND 14
3 C14
+
C15
VBG
D[0:13] A[0:1] 2 35 36 37 CSB
AGND
4 C16
CML
OEB WRB
CONTROL BUS
AGND
5 C17
+
C18
REF+
AGND
6 C19
+
C20
REF-
OVI
10
OUT OF RANGE INDICATOR
AGND
Figure 13 External Components Diagram
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PD Rev 1.1 February 2001
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Production Data
WM2148
SUGGESTED VALUE 10F 0.1F 470pF 0.1F 470pF 0.1F 470pF 10F 0.1F 0.1F 0.1F 0.1F 10F 0.1f DESCRIPTION Analogue Supply Decoupling Supply Decoupling for Reference Block Supply Decoupling for Reference Block - place as close to the IC as possible Supply Decoupling for ADC Supply Decoupling for ADC - place as close to the IC as possible Supply Decoupling for ADC Op-amps Supply Decoupling for ADC Op-amps - place as close to the IC as possible (most critical for ADC performance) Digital Supply Decoupling Supply Decoupling Clock Buffers - place as close to the IC as possible to eliminate clock jitter Supply Decoupling for Core Logic Supply Decoupling for Control Block Supply Decoupling for Output Drivers Reference Decoupling Reference Decoupling - place as close to the IC as possible
COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12, C13 C14, C17, C19 C15, C16, C18, C20
Table 6 External Components Values and Description
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PD Rev 1.1 February 2001
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WM2148 PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C
Production Data
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
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